The present invention relates to an on die termination (ODT) control circuit configured to control ODT operation of a semiconductor memory device, and more particularly, to an ODT control circuit with low power consumption.
With increasing capacity/speed of semiconductor memory devices, particularly DRAMs, and the advent of double data rate (DDR) synchronous DRAMs (SDRAMs), new technical ideas have been suggested to increase a transmission rate in memory devices. As one of various technical ideas, a termination resistor is required to enhance signal transmission between devices.
If impedance is not matched properly, a transmitted signal may be reflected, leading to an error of signal transmission. If, however, a fixed resistor is employed, the impedance cannot be properly matched due to degradation of an integrated circuit (IC), temperature variation or fabrication process variation. Therefore, to compare the resistance of a termination resistor with that of an external reference resistor and make them equal to each other, an impedance matching technology recently has been proposed, which controls a termination resistor by adjusting the number of turned-on transistors among a plurality of transistors connected in parallel.
An on-die termination (ODT) control circuit is a circuit to be used for controlling enabling/disabling timings of ODT operation, that is, enabling/disabling timings of an ODT circuit. Such an ODT control circuit is disclosed in Korean Patent Registration No. 10-0625298.
According to the JEDEC standard, dynamic termination operation must be supported in DDR3 SDRAMs or high-grade memory devices. The dynamic termination operation is the operation of setting a termination resistor in a chip to have a predetermined resistance required to input data when a write command is input even though a mode register set (MRS) is not set again.
A data-input interface of a semiconductor memory device differs in the termination method and resistance of a termination resistor from a data-output interface. When data are output, an input/output pad, e.g., DQ pad, is pull-up or pull-down terminated to output data of logic ‘High’ or ‘Low’. In contrast, when data are input, the semiconductor memory device receives the data in a state that the input/output pad is pull-up and pull-down terminated to a predetermined resistance, which differs from the resistance when the data are output. Termination schemes in data input/output may be differently designed depending on a kind of a memory device. In DDR3 SDRAMs or high-grade memory devices supporting dynamic termination operation, an ODT circuit inside a chip appositely operates just by receiving a write command.
That is, ODT control circuits before the advent of DDR3 memory devices played a role in simply controlling the ODT circuit to be enabled/disabled, however, dynamic termination operation must be added to DDR3 SDRAMs or high-grade memory devices.
Therefore, the ODT control circuit used in DDR3 memory devices controls enabling/disabling of normal termination operation and enabling/disabling of dynamic termination operation.
FIG. 1 is a block diagram of a conventional ODT control circuit configured to control normal termination operation and dynamic termination operation.
Referring to FIG. 1, the conventional ODT circuit includes a counter 110, a normal termination controller 130, a dynamic termination controller 120, a clock divider 101, and a replica delay line 102. The counter 110 counts an external clock EXTCLK to output a first code EXTCNT<2:0>, and counts an internal clock DLLCLK2 to output a second code DLLCNT<2:0>. The normal termination controller 130 compares the first code EXTCNT<2:0> and the second code DLLCNT<2:0> with each other to determine enabling/disabling timings of normal termination operation in response to termination commands ODT_STARTP and ODT_ENDP. The dynamic termination controller 120 compares the first code EXTCNT<2:0> and the second code DLLCNT<2:0> with each other to determine enabling/disabling timings of dynamic termination operation in response to a write command WT_STARTP. The clock divider 101 supplies the internal clock DLLCLK2 to the ODT control circuit. The replica delay line 102 receives the internal clock DLLCLK2 to generate the external clock EXTCLLK.
The clock divider 101 and the replica delay line 102, which respectively supply the internal clock DLLCLK2 and the external clock EXTCLK to the ODT control circuit, will be described first below.
The clock divider 101 receives an internal clock DLLCLK1 supplied through a delay locked loop (DLL), and prevents the internal clock DLLCLK2 from toggling until a reset RST is deactivated. The clock divider 101 outputs the internal clock DLLCLK2, which is toggling, when the reset signal RST is deactivated. The internal clock DLLCLK2 is the same as the internal clock DLLCLK1 except that the internal clock DLLCLK2 does not toggle until the reset signal RST is deactivated.
The replica delay line 102 models a clock skew between the internal clock DLLCLK and the external clock EXTCLK. The replica delay line 102 reflects the clock skew in the internal clock DLLCLK, and then outputs the external clock EXTCLK.
The counter 110 counts the external clock EXTCLK to output the first code EXTCNT<2:0>, and counts the internal clock DLLCLK2 to output the second code DLLCNT<2:0>. Herein, the first and second codes EXTCNT<2:0> and DLLCNT<2:0> are a binary code. The first code EXTCNT<2:0> is counted from its initial value ‘0’, however, the second code DLLCNT<2:0> has a specific initial value that is determined according to a CAS write latency (CWL). Since the CWL itself is regulated in a specification such that it has a limited value according to an operating frequency, the specific initial value of the second code DLLCNT<2:0> is determined according to the operating frequency.
The dynamic termination controller 120 controls dynamic termination operation. The dynamic termination controller 120 is responsive to the write command WT_STARTP to store the first code EXTCNT<2:0> at a timing when the write command WT_STARTP is activated. The write command WT_STARTP is generated from a write command, which will be described later. The dynamic termination controller 120 compares a stored value of the first code EXTCNT<2:0> and a value of the second code DLLCNT<2:0> to thereby enable the dynamic termination operation at a timing when the values of the two codes are equal to each other. Here, the value of the first code EXTCNT<2:0> does not vary because it is the stored value, but the value of the second code DLLCNT<2:0> increases because it is continuously counted. The dynamic termination operation is disabled at a timing when the sum of the value of the first code EXTCNT<2:0> and a predetermined value determined according to a burst length (BL) of the stored first code EXTCNT<2:0> is equal to the value of the second code DLLCNT<2:0>. Since the value of the stored value of the first code EXTCNT<2:0> is a constant value, the value of the first code EXTCNT<2:0> with the predetermined value added is also a constant value. Operation of the dynamic termination controller 120 will be described in detail with reference to the accompanying drawings later.
The normal termination controller 130 controls normal termination operation. That is, the normal termination controller 130 controls a normal termination operation in response to the termination commands ODT_STARTP and ODT_ENDP provided from an external memory controller. Herein, the termination commands ODT_STARTP and ODT_ENDP are generated by an external command. Operation of the normal termination controller 130 will also be described in detail with reference to the accompanying drawings later.
FIG. 2 illustrates the operation of the dynamic termination controller 120 in FIG. 1.
First, since the internal clock DLLCLK2 and the external clock EXTCLK do not toggle before the reset signal RST is deactivated, the first and second codes EXTCNT<2:0> and DLLCNT<2:0> are not counted but fixed to respective initial values. From FIG. 2, it can be observed that the first code EXTCNT<2:0> has the initial value of 0, and the second code DLLCNT<2:0> has the initial value of 5. As described above, the initial value of the second code DLLCNT<2:0> is determined according to CWL. When the reset signal RST is deactivated, the first and second codes EXTCNT<2:0> and DLLCNT<2:0> start to be counted. The counting of the first code EXTCNT<2:0> is performed later than the counting of the second code DLLCNT<2:0> because the external clock EXTCLK is generated by delaying the internal clock DLLCLK2.
Meanwhile, when a write command is input from the outside, the WT_STARTP pulse signal is activated in response to the write command. The first code EXTCNT<2:0> at an enabling timing of the WT_STARTP pulse signal is stored (1 is stored in FIG. 2). A WT_DLL_STARTBP signal is activated to a logic low level when the value of the second code DLLCNT<2:0> is equal to the stored value of the first code EXTCNT<2:0>, i.e., 1. The WT_DLL_STARTBP signal activates a DYNAMIC OTEN signal used to control the dynamic termination operation, which initiates the dynamic termination operation.
How to finish the dynamic termination operation will be described below. A predetermined value is added to the stored value of the first code EXTCNT<2:0>, i.e., 1, according to a burst length BL in response to the write command. Since eight data are input at rising/falling edges of a clock when the burst length is 8, four clocks are required. In consideration of a timing margin, however, six clocks are required in totality, which is regulated in a specification. When the burst length is 4, four clocks are required in totality because two clocks are used for data input and the other two clocks are used for a timing margin, which is also regulated in a specification.
Therefore, when the burst length is 8, the value of 6 is added to the stored value of the first code EXTCNT<2:0>, i.e., 1. In FIG. 2, the burst length is 8 and thus the added value equals to 7, that is, 1+6=7. When the burst length is 4, the value of 4 is added to the stored value of the first code EXTCNT<2:0>. That is, when the burst length is assumed to be BL, the value of (BL/2)+2 is added to the stored value of the first code EXTCNT<2:0>. Thereafter, the value of the first code EXTCNT<2:0> with the predetermined value added is compared with the value of the second code DLLCNT<2:0>. At a timing when the value, i.e., 7, of the first code EXTCNT<2:0> with the predetermined value added is equal to the value of the second code DLLCNT<2:0>, a WT_DLL_ENDBP signal is activated to a logic low level, which deactivates the DTNAMIC ODTEN signal so that the dynamic termination operation is finished.
In this way, the conventional dynamic termination controller 120 enables the dynamic termination operation after a predetermined time from the input of the write command. After securing a time necessary for data input and a predetermined margin, the dynamic termination is disabled.
FIG. 3 is a timing diagram illustrating the WT_STARTP pulse signal in FIG. 2.
The WT_STARTP pulse signal is basically activated in response to a write command. As illustrated in FIG. 3, a column address strobe (CAS) command corresponding to the write command is input, and then the WT_STARTP pulse signal is activated after a predetermined time, i.e., after an additive latency (AL). Herein, since the CAS command corresponds to the write command, the CAS command is input while a write enable signal WE is activated.
In detail, when an external CAS command corresponding to the write command is input, a command input buffer receives the CAS command in synchronization with a clock CLK. Thereafter, the CAS command is delayed by a predetermined delay time tD1 in an internal circuit, and then the WT_STARTP pulse signal is activated. That is, the write pulse signal WT_STARTP may be generated by delaying the write command from the outside by a predetermined delay time. For reference, a pulse width of the WT_STARTP pulse signal may be properly set in consideration of a margin.
FIG. 4 illustrates operation of the normal termination controller 130 in FIG. 1.
First, since the internal clock DLLCLK2 and the external clock EXTCLK do not toggle before the reset signal RST is deactivated, the first and second codes EXTCNT<2:0> and DLLCNT<2:0> are not counted but fixed to respective initial values. From FIG. 4, it can be observed that the first code EXTCNT<2:0> has the initial value of 0, and the second code DLLCNT<2:0> has the initial value of 5. As described above, the initial value of the second code DLLCNT<2:0> is determined according to CWL. When the reset signal RST is deactivated, the first and second codes EXTCNT<2:0> and DLLCNT<2:0> start to be counted. The counting of the first code EXTCNT<2:0> is performed later than the counting of the second code DLLCNT<2:0> because the external clock EXTCLK is generated by delaying the internal clock DLLCLK2.
Meanwhile, an ODT_STARTP signal is activated, which is generated by a termination command of an external memory controller (also referred to as a ‘chipset’). The first code EXTCNT<2:0> at an enabling timing of the ODT_STARTP signal is stored (1 is stored in FIG. 4). An ODT_DLL_STARTBP signal is activated to a logic low level when the value of the second code DLLCNT<2:0> is equal to the stored value of the first code EXTCNT<2:0>, i.e., 1. This ODT_DLL_STARTBP signal activates an ODTEN signal used to control normal termination operation, which initiates the normal termination operation. The normal termination operation means a typical termination operation, not the dynamic termination operation.
The finish of the normal termination operation is performed in the same manner as the initiation of the normal termination operation. The value of the first code EXTCNT<2:0> at an enabling timing of the ODT_ENDP signal generated by the termination command of the external memory controller is stored, for example, the value of 6 is stored in FIG. 4. When the value of the second code DLLCNT<2:0> is equal to the stored value of the first code EXTCNT<2:0>, e.g., 6, an ODT_DLL_ENDBP signal is activated to a logic low level, which deactivates the ODTEN signal used to control the normal termination operation. Finally, the normal termination operation is finished.
That is, both the initiation and finish of the normal termination operation are controlled by the external memory controller.
FIG. 5 is a timing diagram illustrating the ODT_STARTP signal and the ODT_ENDP signal.
The ODT_STARTP signal and the ODT_ENDP signal are basically generated by a command from the external memory controller. The termination command ODT is applied from the memory controller so as to satisfy setup/hold conditions. The termination command ODT is synchronized with an internal clock and then delayed by a predetermined time, i.e., additive latency (AL), thereby generating an ODT_COM signal. The ODT_STARTP signal and the ODT_ENDP signal are respectively activated at the enabling and disabling timings of the ODT_COM signal. Here, the ODT_STARTP signal and the ODT_ENDP signal are pulse-type signals.
As described above, the conventional ODT control circuit compares the first code EXTCNT<2:0> generated by counting the external clock EXTCLK with the second code DLLCNT<2:0> generated by counting the internal clock DLLCLK2, thus controlling the normal termination operation and the dynamic termination operation. Such a conventional ODT control circuit keeps on counting the external clock EXTCLK and the internal clock DLLCLK2 to generate the first code EXTCNT<2:0> and the second code DLLCNT<2:0>. Accordingly, the counter 110 consumes current continuously.
Furthermore, since the first and second codes EXTCNT<2:0> and DLLCNT<2:0>, which are continuously toggling, i.e., varying, are input into the normal termination controller 130 and the dynamic termination controller 120 for comparison, gate terminals of logic gates in the normal termination controller 130 and the dynamic termination controller 120 are charged and discharged continuously, thus always giving rise to a dynamic current consumption. This means that a memory device unnecessarily consumes power even in a stand-by mode.
For reference, dynamic power consumption means power consumption caused by charging/discharging of loading capacitors while a circuit is operating. More particularly, dynamic power consumption means power consumption occurring while capacitors at gate terminals are being charged and discharged periodically due to continuous toggling of the first and second codes EXTCNT and DLLCNT<2:0>.
Recently, there has been increasing demand for a low-power semiconductor memory device. In particular, power consumption in a stand-by mode may basically affect power consumption of all operating modes, and thus technology for reducing power consumption in a stand-by mode is a critical issue in semiconductor memory devices.